View HB52R1289E2U-A6B_5067048.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HB52R1289E2U-A6B/B6B
1 GB Registered SDRAM DIMM 128-Mword x 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M x 4 Components) PC100 SDRAM
EO
Description Features
E0016H10 (1st edition) (Previous ADE-203-1194A (Z)) Preliminary Jan. 30, 2001
The HB52R1289E2U belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. The HB52R1289E2U is a 64M x 72 x 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM (HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R1289E2U is 168-pin socket type package (dual lead out). Therefore, the HB52R1289E2U makes high density mounting possible without surface mount technology. The HB52R1289E2U provides common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
* Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev. 1.2) * 168-pin socket type package (dual lead out) Outline: 133.35 mm (Length) x 30.48 mm (Height) x 4.80 mm (Thickness) Lead pitch: 1.27 mm * 3.3 V power supply * Clock frequency: 100 MHz (max) * LVTTL interface * Data bus width: x 72 ECC * Single pulsed RAS Preliminary: The Specifications of this device are subject to change without notice. Please contact to your nearest Elpida Memory, Inc.regarding specifications.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
This product became EOL in September, 2002.
Pr
od
t uc
HB52R1289E2U-A6B/B6B
* * * * 4 Banks can operates simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence Sequential Interleave Programmable CE latency : 3/4 (HB52R1289E2U-A6B) : 4 (HB52R1289E2U-B6B) Byte control by DQMB Refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh
EO
* * * *
Ordering Information
Type No. HB52R1289E2U-A6B HB52R1289E2U-B6B
Pin Arrangement
L
Frequency 100 MHz 100 MHz 4
CE latency 3/4
Package
Contact pad
168-pin dual lead out socket type Gold
1 pin 10 pin 11 pin
85 pin 94 pin 95 pin 124 pin 125 pin
Preliminary Data Sheet E0016H10 2
Pr
40 pin 41 pin
od
84 pin 168 pin
t uc
HB52R1289E2U-A6B/B6B
Pin No. 1 2 3 4 5 6 7 8 9 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC Pin No. 43 44 45 46 47 Pin name VSS NC S2 DQMB2 DQMB3 NC VCC NC NC CB2 CB3 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Pin name VSS CKE0 S3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58
EO
48 DQ4 DQ5 DQ6 49 50 51 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 DQ7 DQ8 VSS DQ9 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC W DQMB0 DQMB1 S0 NC VSS A0 A2 A4
L
VSS VCC NC NC NC VSS VSS VCC
DQ16 DQ17 DQ18 DQ19
Preliminary Data Sheet E0016H10 3
Pr
101 DQ20 102 VCC 103 104 105 CB4 106 CB5 VSS DQ21 DQ22 DQ23 107 108 109 NC NC 110 VCC DQ24 DQ25 DQ26 DQ27 111 CE 112 113 114 115 116 117 118 119 S1 RE VSS A1 A3 A5 DQ28 DQ29 DQ30 DQ31
DQ45
DQ46 DQ47
od
149 150 151 152 153 DQMB4 DQMB5 154 155 156 157 158 159 160 161
t uc
DQ59 VCC DQ60 DQ61 DQ62 DQ63
HB52R1289E2U-A6B/B6B
Pin No. 36 37 38 39 40 41 42 Pin name A6 A8 A10 (AP) BA1 VCC VCC Pin No. 78 79 80 Pin name VSS CK2 NC WP SDA SCL VCC Pin No. 120 121 122 123 124 125 126 Pin name A7 A9 BA0 A11 VCC CK1 A12 Pin No. 162 163 164 165 166 167 168 Pin name VSS CK3 NC SA0 SA1 SA2 VCC
EO
81 82 83 CK0 84
Pin Description
Pin name A0 to A12
L
Function Address input Row address Column address Bank select address A0 to A12 A0 to A9, A11 BA0/BA1
BA0/BA1 DQ0 to DQ63 CB0 to CB7 S0 to S3 RE CE W DQMB0 to DQMB7 CK0 to CK3 CKE0 WP REGE* SDA SCL SA0 to SA2 VCC VSS NC Note:
1
1. REGE is the Register Enable pin which permits the DIMM to operate in "buffered" mode and "registered" mode. To conform to this specification, mother boards must pull this pin to high state ("registerd" mode).
Preliminary Data Sheet E0016H10 4
Pr
Data input/output Chip select input Row enable (RAS) input Write enable input Byte data mask Clock input Clock enable input Write protect for serial PD Register enable Clock input for serial PD Serial address input Ground No connection
Check bit (Data input/output)
Column enable (CAS) input
Data input/output for serial PD
Primary positive power supply
od t uc
HB52R1289E2U-A6B/B6B
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 80 08 04 0D 0B 02 48 00 01 A0 128 256 byte SDRAM 13 11 2 72 bit 0 (+) LVTTL CL = 3
EO
Number of banks Module data width SDRAM cycle time (highest CE latency) 10 ns 10 11 12 Refresh rate/type 13 14 15 SDRAM width 16 17 18 (-B6B) 19
Number of row addresses bits
Number of column addresses bits
Module data width (continued) Module interface signal levels
SDRAM access from Clock (highest CE latency) 6 ns Module configuration type
Error checking SDRAM width
SDRAM device attributes: 0 minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CE latency (-A6B) 0 0
SDRAM device attributes: S latency
L
0 0 1 0 0 0 0 0
1
1
0
0
0
0
0
60
*3
Preliminary Data Sheet E0016H10 5
Pr
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0
1 1
0 0
02 82
ECC Normal (7.8125 s) Self refresh 64M x 4 x4 1 CLK
0 0 0
0 0 1
04 04 01
od
1 0 1 0 0F 04 1 0 06 0 0 0 04 1 01
1, 2, 4, 8 4
t uc
2/3 3 0
HB52R1289E2U-A6B/B6B
Byte No. Function described 20 21 22 23 SDRAM device attributes: W latency SDRAM device attributes SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) (-A6B) 10 ns (-B6B) Undefined Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 01 16 0E A0 0 Registered VCC 10% CL = 2
EO
24 (-B6B) Undefined 25 26 27 28 29 30 31 32 33 34 35 RE to CE delay min 36 to 61 Superset information 62 63 (-B6B) 64 72 6
0 0
0 1
0 1
0 0
0 0
0 0
0 0
0 0
00 60
SDRAM access from Clock (2nd highest CE latency) (-A6B) 6 ns
0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
00 00
SDRAM cycle time (3rd highest CE latency) Undefined
SDRAM access from Clock (3rd highest CE latency) Undefined
Minimum row precharge time Row active to row active min
Minimum RE pulse width
Density of each bank on module 1 Address and command signal input setup time Address and command signal input hold time Data signal input setup time Data signal input hold time 0 0 0 0 0 0
SPD data revision code Checksum for bytes 0 to 62 (-A6B)
Manufacturer's JEDEC ID code
65 to 71 Manufacturer's JEDEC ID code Manufacturing location
L
0 0 0 0 0 0 0 0 0 0 x
0
0
0
0
0
0
0
00
Preliminary Data Sheet E0016H10
Pr
0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 1 0 1 0 0 0 0 0 0 0 x 1 0 0 1 0 1 0 1 1 1 0 0 x 0 0 0 0 0 0 0 0 1 1 0 0 x 0 0 0 0 0 0 0 0 0 0 1 0 x
0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 x
0 0 0 0 0 0 0 0 0 0 0
14 14 14 32 80 20 10 20 10 00 12
20 ns 20 ns 20 ns 50 ns 2 bank 512M byte 2 ns* 3 1 ns* 3 2 ns* 3 1 ns* 3 Future use Rev. 1.2A
od
1 1B 1 19 1 0 x 07 00 xx
t uc
27 25 HITACHI * 4 (ASCII8bit code)
HB52R1289E2U-A6B/B6B
Byte No. Function described 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 x x 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 x x 48 42 35 32 52 31 32 38 39 45 32 55 2D 41 42 36 42 20 20 30 20 xx xx H B 5 2 R 1 2 8 9 E 2 U -- A B 6 B (Space) (Space) Initial (Space) Year code (BCD)*5 Week code (BCD) *5
EO
(-B6B) 87 88 89 90 91 92 93 94 Revision code Revision code Manufacturing date Manufacturing date 126 127 (-B6B)
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacture's part number
Manufacturer's part number (-A6B)
Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data Intel specification frequency Intel specification CE# latency support (-A6B)
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on Intel specification (Rev.1.2A). 2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119. 3. Byte10, 23, 24, 32 through 35 are component spec. 4. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.)
L
0 0 0 0 0 0 0 0 x x *7 -- 0 1 1
Preliminary Data Sheet E0016H10 7
Pr
0 1 0 0 0 0 x x 1 0 1 1 1 1 x x 1 0 0 0 1 0 x x 0 0 0 0 0 0 x x 1 0 0 0 0 0 x x -- 1 0 -- 1 0 -- 0 0 -- 0 0 -- 1 1 0 0 0 0 1
od
-- 0 1 -- 0 1 -- 64 87 0 1 85
*6 100 MHz
t uc
CL = 2/3 CL = 3
HB52R1289E2U-A6B/B6B
5. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary Coded Decimal". 6. All bits of 99 through 125 are not defined ("1" or "0"). 7. Bytes 95 through 98 are assembly serial number.
EO L
Preliminary Data Sheet E0016H10 8
Pr od t uc
HB52R1289E2U-A6B/B6B
Block Diagram
RS0 RS1 RDQMB0 RDQMB4 DQMB CS I/O0 to I/O3 DQMB CS I/O0 to I/O3 DQMB CS 4 DQ32 to DQ35 10 I/O0 to I/O3 DQMB CS I/O0 to I/O3
EO
4 DQ0 to DQ3 10 4 DQ4 to DQ7 10 RDQMB1 4 10 DQ8 to DQ11 4 10 DQ12 to DQ15 CB0 to CB3 4 10 RS2 RS3 RDQMB2 4 DQ16 to DQ19 10 DQ20 to DQ23 RDQMB3 10 4 10 4 DQ24 to DQ27 4 DQ28 to DQ31 10 S0, S1, S2, S3 DQMB0 to DQMB7 BA0 to BA1 A0 to A12 RE CE CKE0 W VCC REGE PLL CK 10k R E G I S T E R
D0
D18
D9
D27
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS 4 DQ36 to DQ39 RDQMB5 10 I/O0 to I/O3
DQMB CS I/O0 to I/O3
D1
D19
D10
D28
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS 4 DQ40 to DQ43 10 I/O0 to I/O3
DQMB CS I/O0 to I/O3
D2
D20
D11
D29
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS 4 DQ44 to DQ47 10 I/O0 to I/O3
DQMB CS I/O0 to I/O3
SA0 SA1 SA2 VSS Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
L
D3
DQMB CS I/O0 to I/O3
D21
D12
D30
DQMB CS I/O0 to I/O3
DQMB CS CB4 to CB7 4 10 I/O0 to I/O3
DQMB CS I/O0 to I/O3
D4
D22
D13
D31
RDQMB6
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
RS0, RS1, RS2, RS3 RDQMB0 to RDQMB7 RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 CK1 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35 to CK3 RRAS -> RAS: SDRAMs D0 to D35 RCAS -> CAS: SDRAMs D0 to D35 VCC RCKE0 -> CKE: SDRAMs D0 to D35 0.0022 F x 26 pcs RW -> WE: SDRAMs D0 to D35 VSS Serial PD SCL SCL SDA SDA WP A2 47 k
Preliminary Data Sheet E0016H10 9
Pr
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
D5
D23
4
10
D14
D32
DQ48 to DQ51
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
D6
D24
DQ52 to DQ55
4
10
D15
D33
RDQMB7
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3
od
4 10
D7
D25
D16
D34
DQ56 to DQ59
DQMB CS I/O0 to I/O3
DQMB CS I/O0 to I/O3 R1
DQMB CS I/O0 to I/O3
D8
D26
4
10
D17
D35
DQ60 to DQ63
CK0
PLL 12 pF
CK : SDRAMs (D0 to D35) Register
R2 to R4
VSS
12 pF
U0
A0 A1
* D0 to D35: HM5225405 PLL: 2510 Register: 16834 U0: 2-kbit EEPROM
t uc
VCC (D0 to D35, U0) 0.22 F x 19 pcs VSS (D0 to D35, U0)
HB52R1289E2U-A6B/B6B
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 18.0 0 to +55 -50 to +100 Unit V V mA W C C Note 1 1
EO
Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS Parameter Supply voltage Input high voltage Input low voltage Ambient illuminance Notes: 1. 2. 3. 4. 5. 10
DC Operating Conditions (Ta = 0 to +55C)
Symbol VCC Min 3.0 0 2.0 0 Max 3.6 0 VCC 0.8 Unit V V V V lx Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS The supply voltage with all VCC and V CCQ pins must be on the same level. The supply voltage with all VSS and VSS Q pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
L
--
VSS VIH VIL
Preliminary Data Sheet E0016H10
Pr
-- 100
od t uc
HB52R1289E2U-A6B/B6B
VIL/VIH Clamp (Component characteristics)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins.
I (mA)
EO
VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 0 -2 -5 -10 -15 -20 -25 -30 -35
Minimum VIL Clamp Current
I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0 0
L
-1.5
Preliminary Data Sheet E0016H10 11
Pr
0 0 -1 VIL (V)
-0.5
0
od t uc
HB52R1289E2U-A6B/B6B
Minimum VIH Clamp Current (referred to VIH)
VIH (V) VCC + 2 I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
I (mA)
EO
VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 0 VCC + 0
L
10 8 6 4 2 VCC + 0.5
Preliminary Data Sheet E0016H10 12
Pr
VCC + 1
od
VCC + 1.5 VCC + 2 VIH (V)
t uc
HB52R1289E2U-A6B/B6B
IOL/IOH Characteristics (Component characteristics)
Output Low Current (IOL)
IOL (mA)
EO
Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 50 0 0 0.5
I OL Min (mA) 0 27 41 51 58 70 72
I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
L
75 77 77 80 81 1 1.5 2 Vout (V) 2.5 Preliminary Data Sheet E0016H10
Pr
od
3 3.5
min max
t uc
13
HB52R1289E2U-A6B/B6B
Output High Current (I OH ) (Ta = 0 to 55C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH Vout (V) Min (mA) -- -- 0 -21 -34 -59 -67 -73 -78 -81 -89 -93 I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
IOH (mA)
EO
3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 0 0 0.5 -100 -200 -300 -400 -500 -600 14
L
1 1.5 2 2.5 Vout (V) Preliminary Data Sheet E0016H10
Pr
3
3.5
od
min max
t uc
HB52R1289E2U-A6B/B6B
DC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52R1289E2U -A6B Min -- -- -- -- -- -- -- Max 2945 2945 803 767 1415 839 1775 -B6B Min -- -- -- -- -- -- -- Max -- 2945 803 767 1415 839 1775 Unit mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, S = VIH, t CK = 12 ns CKE = VIL, t CK = 12 ns CKE, S = VIH, t CK = 12 ns t CK = min, BL = 4 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
EO
Parameter Operating current (CE latency = 3) (CE latency = 4) I CC1 I CC1 Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CE latency = 3) (CE latency = 4) Refresh current (CE latency = 3) (CE latency = 4) Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage I CC4 I CC4 I CC5 I CC5 I CC6 I LI I LO VOH VOL
Symbol
Standby current in power I CC2P down Standby current in power I CC2PS down (input signal stable) I CC2N I CC3P
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
L
I CC3N -- -- -- -- -- -10 -10 2.4 --
Preliminary Data Sheet E0016H10 15
Pr
2945 2945 5195 5195 803 -- -- -- -- -- -- 2945 -- 5195 803 10 10 10 10 -- 0.4 -10 -10 2.4 -- A A -- V 0.4 V
mA mA t RC = min 3
mA mA mA VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC 8
od
I OH = -4 mA I OL = 4 mA
0 Vout VCC DQ = disable
t uc
HB52R1289E2U-A6B/B6B
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1 Max 25 25 45 20 45 20 25 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
EO
Input capacitance (RE, CE, W) Input capacitance (CKE) Input capacitance (S) Input capacitance (CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4. Parameter System clock cycle time (CE latency = 3) (CE latency = 4) CK high pulse width CK low pulse width Access time from CK (CE latency = 3) (CE latency = 4) Data-out hold time CK to Data-out low impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time 16
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V)
CK to Data-out high impedance
CKE setup time for power down exit
L
t CK t CK t AC t AC t OH t LZ t HZ t DS t DH t AS t AH
Preliminary Data Sheet E0016H10
Pr
Symbol PC100 Symbol Min Tclk Tclk Tch Tcl 10 10 t CKH t CKL 4 4 Tac Tac -- -- Toh 2.1 1.1 -- Tsi Thi Tsi Thi Tsi Tpde 2.9 3.4 2.6 3.0 2.6 2.6 t CES t CESP
HB52R1289E2U -A6B/B6B Max -- -- -- -- Unit ns ns ns ns Notes 1
od
7.5 7.5 -- -- ns ns ns ns 7.5 -- -- -- -- -- -- ns ns ns ns ns ns ns
1 1 1, 2
1, 2 1, 2, 3 1, 4
t uc
1 1 1 1, 5 1, 5 1
HB52R1289E2U-A6B/B6B
AC Characteristics (Ta = 0 to 55C, VCC = 3.3 V 0.3 V, VSS = 0 V) (cont)
HB52R1289E2U -A6B/B6B
EO
Parameter CKE hold time Command setup time Command hold time Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5.
Symbol t CEH t CS t CH
PC100 Symbol Thi Tsi Thi Trc Tras Trcd Trp Tdpl Trrd
Min 3.0 2.6 3.0 70 50 20 20 20 20 1
Max -- -- -- -- 120000 -- -- -- -- 5 64
Unit ns ns ns ns ns ns ns ns ns ns ms
Notes 1 1 1 1 1 1 1 1 1
Ref/Active to Ref/Active command period t RC Active to precharge command period Active command to column command (same bank) Precharge to active command period t RAS t RCD t RP
Write recovery or data-in to precharge lead time
Active (a) to Active (b) command period
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
L
tT 2.4 V 0.4 V 2.0 V 0.8 V t
T
t DPL t RRD
Pr
t REF -- tT
od
DQ
Test Conditions
* Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures * Ambient illuminance: Under 100 lx
t uc
CL 17
input
Preliminary Data Sheet E0016H10
HB52R1289E2U-A6B/B6B
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) HB52R1289E2U -A6B/B6B PC100 Symbol Symbol 10 I RCD I RC I RAS I RP I DPL I RRD I SREX I APW I SEC Tsrx Tdal Tdpl 2 7 5 2 2 2 2 4 7 Notes 1 = [IRAS + IRP] 1 1 1 1 1 2 = [IDPL + IRP] = [IRC] 3
EO
Self refresh exit time (CE latency = 4) (CE latency = 4) DQMB to data in DQMB to data out CKE to CK disable S to command disable (CE latency = 4) 18
Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank)
Last data in to active command (Auto precharge, same bank)
Self refresh exit to command input
Precharge command to high impedance (CE latency = 3)
Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CE latency = 3)
Column command to column command Write command to data in latency
Register set to active command
Power down exit to command input Burst stop to output valid data hold (CE latency = 3)
L
Preliminary Data Sheet E0016H10
Pr
I HZP I HZP Troh Troh I APR I EP I EP I CCD Tccd I WCD Tdwd I DID Tdqm Tdqz Tcke Tmrd I DOD I CLE I RSA I CDD I PEC I BSR I BSR
3 4 0 -2 -3 1 1
od
1 3 2 1 0 1 2 3
t uc
HB52R1289E2U-A6B/B6B
Parameter Frequency (MHz) tCK (ns) HB52R1289E2U -A6B/B6B PC100 Symbol Symbol 10 I BSH I BSH I BSW 3 4 1 Notes
EO
(CE latency = 4) Burst stop to write data ignore
Burst stop to output high impedance (CE latency = 3)
Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP]
L
Preliminary Data Sheet E0016H10 19
Pr od t uc
HB52R1289E2U-A6B/B6B
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is precharged. BA0/BA1 (input pin): BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is High, bank 3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
EO
Detailed Operaion Part
20
REGE (input pins): If REGE is High, the register is registered mode. If REGE is Low, the register is buffered mode.
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.
L
Preliminary Data Sheet E0016H10
Pr
od
t uc
HB52R1289E2U-A6B/B6B
Physical Outline
Unit: mm inch 133.35 5.25 (DATUM -A-) 4.80 max 0.189 max
Front side
4.00 0.157
17.80 0.70 1.00 0.039 0.123 0.005
Component area (Back)
(DATUM -A-)
Detail A 2.50 0.20 0.098 0.008 0.20 0.15 0.010 0.0004 1.27 0.050
Detail B R FULL
Detail C
(DATUM -A-)
R FULL
3.125 0.125
0.123 0.005
3.125 0.125
6.35 0.250 2.00 0.10 0.079 0.004
1.00 0.05 0.039 0.002
6.35 0.250 4.175 0.164 2.00 0.10 0.079 0.004
Note: Tolerance on all dimensions 0.15/0.006 unless otherwise specified.
ED480120W
Preliminary Data Sheet E0016H10 21
30.48 1.20
168
EO
3.00 0.118 3.00 0.118 1 C 11.43 0.450 Back side 2 - 3.00 2 - 0.118 85
(63.67) (2.51)
Component area (Front)
84 B 54.61 2.150 A
36.83 1.450
1.27 0.050
127.35 5.014
4.00 min 0.157 min
L
Pr
od
t uc
HB52R1289E2U-A6B/B6B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
EO
22
L
Preliminary Data Sheet E0016H10
Pr
od
t uc

▲Up To Search▲

Price & Availability of HB52R1289E2U-A6B

	To Download HB52R1289E2U-A6B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .